Weekly Digest 31

Topics we are tracking

China starts producing its own immersion DUV machines

Source: Reuters — China starts production of home-grown immersion DUV chipmaking tools, source says

China has started producing its first domestically developed immersion deep-ultraviolet lithography machines. According to Reuters, the effort is being led by Shanghai Aishengna Electronic Technology Group, a state-owned company established in 2023. Aishengna has incorporated teams from Yuliangsheng and Shanghai Micro Electronics Equipment, two of China's domestic lithography programmes. The company reportedly plans to produce around five machines in 2026 and 20 in 2027, with initial systems expected to be delivered to SMIC, Hua Hong and memory manufacturer CXMT.

The report sent ASML shares down 8%, which is the market overreacting to the headline and taking these claims at face value. China still depends on foreign lithography machines for advanced chip production, which remains the biggest chokepoint in its ability to scale advanced-node capacity. But they are only one part of the semiconductor manufacturing equipment stack. A fab also needs deposition, etch, ion implantation, cleaning, metrology and inspection equipment, much of which is also subject to export restrictions.

Leading-edge fabs in the US, Taiwan and South Korea use both EUV and immersion DUV lithography for advanced-node production. ASML has a complete monopoly in EUV and a near-monopoly in immersion DUV. China has never been allowed to import EUV systems and is now also restricted from purchasing several of ASML's most advanced immersion DUV models.

China has demonstrated that it can produce 7-nanometre-class chips using imported ASML immersion DUV machines and extensive multipatterning. But the process is substantially less economical than EUV-based production. Previous industry estimates suggested that SMIC's 5-nanometre and 7-nanometre processes could cost 40–50% more than comparable TSMC production, with reported yields for some 7-nanometre products at a third of TSMC's.

Based on the news, we have moved forward our timeline slightly for domestic Chinese immersion DUV, but are assigning only limited additional advanced-node capacity. If Aishengna delivers functioning machines in 2026 and qualifies them during 2027, they could initially become useful at 28 nanometres and other relatively mature process nodes. The effect on sub-10-nanometre capacity is unlikely to materialise until later.

Advanced-node production requires much tighter overlay accuracy, better stage control, higher-quality optics, more sophisticated computational lithography and an entire process flow tuned around the scanner. Earlier reporting suggested that integration into production lines could begin in 2027, while genuinely domestic sub-10-nanometre production may remain several years further away.

It is no surprise that China is trying to remove one of its largest technological bottlenecks. But the Reuters report relies on anonymous sources; the machines still require further testing and remain far behind ASML's systems. For reference, ASML shipped its first EUV prototypes in 2006, yet the technology did not enter high-volume manufacturing until 2019. Immersion DUV is less complex, but there is still likely to be a meaningful delay between producing an early machine and operating it reliably at commercial scale.

Nvidia's bet on the open-weight ecosystem

Source: The Information — Nvidia's Bet on Reflection, the Open-Source AI Startup Now Playing Catch-Up

The Information reported how Reflection AI is increasingly playing catch-up as Chinese labs continue to release increasingly capable open models. Reflection was founded in 2024 by former Google DeepMind researchers Misha Laskin and Ioannis Antonoglou. The company initially focused on autonomous software engineering before expanding its ambitions to building frontier open-weight foundation models. Since then, it has raised billions of dollars, signed multi-billion-dollar compute agreements and positioned itself as an American alternative to the growing wave of Chinese open models.

Nvidia has invested in Reflection and more broadly is heavily investing in the open weights ecosystem. It committed $5 billion to Ilya Sutskever's Safe Superintelligence (SSI), launched its own Nemotron family of open models and recently announced the Nemotron Coalition, bringing together companies including Mistral, Perplexity, Reflection, Cursor and others to develop open frontier models. Last week, Jensen Huang also made his first post on X to share an industry letter opposing restrictions on open-weight models. The letter argued that open models strengthen cybersecurity, accelerate innovation and allow companies and governments to build AI systems without depending entirely on a small number of closed providers.

Closed-model providers such as Anthropic, Google and OpenAI generate enormous demand for Nvidia GPUs, either directly or through their cloud partners. But as these labs scale, they have a growing incentive to vertically integrate. Google trains Gemini primarily on its own TPUs. Amazon is developing Trainium while investing heavily in Anthropic. OpenAI has partnered with Broadcom on a custom inference chip and a broader shift towards custom inference silicon is already under way.

Custom silicon may reduce the labs' dependence on Nvidia, but it does not allow them to capture the significantly higher margin. Nvidia reported a gross margin of roughly 75% in its latest quarter, while Broadcom's consolidated gross margin was about 69%. Broadcom does not disclose the margin of its custom AI-chip business separately, but the company still captures a substantial part of the economics as the chip designer and supplier. The important advantage is tighter hardware–software co-design. A chip designed around a specific model architecture and inference workload can offer better performance and lower cost than a general-purpose accelerator.

Rental prices for older generation Hopper GPUs have remained high, and Hopper continues to run a large share of inference workloads even as Blackwell and newer generations enter the market. Rapid growth in inference demand, reinforced by falling costs per token, could extend the useful economic life of these GPUs beyond what was initially expected. Nvidia also retains an advantage through software such as TensorRT-LLM, which remains widely used for optimising production inference on its hardware.

Nvidia could also pursue Nemotron more aggressively and attempt to compete directly at the model frontier. But doing so would currently risk competing with some of its largest customers while moving into a business with less attractive economics than selling the infrastructure. For now, Nvidia is better served by supporting a broad model ecosystem. That calculation could change if the largest labs become more successful at reducing their dependence on Nvidia hardware.

Jensen has long advocated for what he calls “sovereign AI”, countries building domestic compute capacity rather than relying entirely on foreign providers for access to intelligence. More recently, Nvidia and Palantir have extended a similar argument to enterprises. Companies should not be entirely dependent on a small number of frontier laboratories for access to models, data and inference infrastructure. Most companies will not have the technical expertise to train or operate their own models. That makes Palantir's position partly self-interested in an attempt to boost its commercial offering. The underlying argument, however, is true: as models become more deeply integrated into corporate operations, dependence on a single external model provider creates risks around pricing, availability and data governance.

Nvidia's ideal outcome is a market where no single company controls the model layer. The more competitive and fragmented the ecosystem becomes, the larger the market for the infrastructure underneath it.

TSMC expands its packaging roadmap

Source: The Information — TSMC Develops AI Chip Packaging Tech to Counter Intel

It was reported this week that TSMC is developing a new advanced packaging architecture designed to compete more directly with Intel's EMIB technology. According to the report, Nvidia is evaluating Intel's packaging for a future AI processor, while Google is considering it for future TPU generations. TSMC is reportedly working with substrate manufacturer Kinsus on a competing solution.

Advanced packaging combines multiple compute dies, HBM stacks and I/O dies inside a single package. As accelerators continue to grow beyond the reticle limit, package architecture determines memory capacity, bandwidth, yield, manufacturing cost and ultimately system performance.

TSMC remains the clear market leader through CoWoS and continues to expand capacity. Intel's EMIB replaces the large silicon interposer used in traditional CoWoS with smaller embedded silicon bridges, reducing the amount of silicon required for certain package designs. The architecture is particularly attractive as package sizes continue to increase.

TSMC already offers CoWoS-L, which also uses local silicon bridges. The difference is that Intel embeds the bridges directly into the package substrate rather than inside a separate redistribution layer. The reported project appears aimed at closing that architectural gap rather than fundamentally changing TSMC's packaging strategy.

Advanced packaging gives Intel a more credible route into the AI supply chain than trying to win leading-edge wafer production from TSMC. Customers can continue manufacturing logic dies at TSMC while outsourcing packaging to Intel. TSMC has expanded CoWoS output aggressively, but demand continues to exceed supply and Nvidia has secured a large share of available capacity. That leaves Google and other custom-chip developers looking for a second packaging source if they want to scale production without depending entirely on TSMC's allocation decisions.

Intel's next-generation EMIB-T architecture adds through-silicon vias and capacitors to the embedded bridges, allowing them to carry high-density signals while also improving power delivery. Intel says this reduces DC voltage drop by 68–80%, which is important for HBM4E, which doubles the number of I/O connections and requires additional power rails. Intel has already validated the technology at tighter bump pitches and is targeting qualification on 4.5-reticle packages by the end of 2026.

TSMC adding a substrate-embedded bridge architecture is perhaps a reaction to this. Future AI packages need to connect and power more compute dies and HBM stacks without scaling a continuous interposer across the entire package. TSMC already offers many of the required technologies across CoWoS-L and its active local interconnect roadmap. The reported Kinsus project would combine those capabilities in a package structure closer to EMIB-T.

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